The chip achieves a peak data transfer rate of 12,800 Mbps, delivering a 60% bandwidth increase over LPDDR5X, which tops out at 10,667 Mbps. Xiaomi has just unveiled its first "mid-folding" phone, the Xiaomi 18 Fold, with a starting price of 10,999 yuan, and the top-tier configuration integrates ChangXin LPDDR6 memory, marking the first time an LPDDR6 product has been commercially adopted in a flagship smartphone worldwide.

This memory solution offers a capacity of 16GB, and with a maximum speed of 12,800 Mbps, it pairs with a system-on-chip (SoC) running at 10,667 Mbps to provide ample data bandwidth, meeting the intense computational demands of flagship smartphones and other high-performance devices. In this release, ChangXin’s LPDDR6 features a single-die capacity of 16Gb, scaling up to a packaged module of 16GB, adhering to the JEDEC LPDDR6 standard and utilizing a new 1295-ball FBGA package.

The chip’s peak transfer rate reaches 12,800 Mbps, which is 60% higher in bandwidth compared to LPDDR5X at 10,667 Mbps. Additionally, power consumption is reduced by 20% versus the previous LPDDR5X generation, effectively extending battery life for mobile devices. Performance metrics are based on internal testing, with the 60% bandwidth boost derived from peak-rate comparisons.

The development and mass production of ChangXin’s LPDDR6 involve several key innovations. On the design front, it adopts a dual-channel architecture with a native 24-bit I/O in standard mode, and its high-speed interfaces support independent tuning of pre-emphasis and decision feedback equalization (DFE) parameters for each signal pin. This, combined with an intelligent training mechanism, ensures signal accuracy and operational stability at high speeds.

For energy efficiency, LPDDR6 employs a dual-rail DVFS design that provides hardware-level voltage isolation. It also introduces a dynamic efficiency mode for strategic scheduling. These capabilities allow the LPDDR6 to maintain an optimal energy-efficiency ratio under varying workloads, offering flexible memory support for devices that balance high computing power with extended battery life.

In terms of reliability, LPDDR6 builds on existing Link ECC and On-Die ECC with new features like per-row activation counting (PRAC) to prevent row hammer attacks and built-in self-test (MBIST) functionality, using multiple safeguards to protect data integrity and system stability.

Process-design co-optimization is another highlight. Through coordinated innovations, over 100 deep optimizations were made to critical CMOS circuits and design rules (LDR), producing smaller, higher-performing CMOS transistors that support the chip’s high-bandwidth, low-power requirements.

On the packaging side, the back-end process uses a 1295-ball FBGA package, which poses greater manufacturing challenges due to a solder ball area that is 50% larger than the 496-ball package used in LPDDR5. In the molding stage, ChangXin applies a high-thermal-conductivity epoxy molding compound (High-K EMC) to fully encapsulate the chip, reducing thermal resistance by approximately 40% and significantly improving heat dissipation during heavy loads to ensure stable performance.

ChangXin Storage’s successful launch of LPDDR6 represents a major milestone in its independent R&D efforts in high-end memory. The product is now accelerating toward broader commercialization and large-scale adoption.